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Graphcore
About Graphcore At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence Job Summary Applicants for this role should have strong experience designing, developing, and maintaining high-quality software systems. The role focuses on testing and validating a complex machine learning software stack, with particular emphasis on software architecture, automation, and engineering best practices. The ideal candidate is an experienced software engineer who values code quality, testability, and long-term maintainability, and enjoys building systems that other engineers rely on. This person will be comfortable working across large codebases, contributing to CI/CD infrastructure, and shaping technical direction through thoughtful design and mentoring in a technically demanding environment spanning ML frameworks, infrastructure, and AI accelerator hardware The Team The ML QA team is composed of highly skilled software engineers with a strong focus on automation, software quality, and data-driven validation. The team works closely with industry-standard machine learning frameworks and models, contributing to upstream open-source projects and collaborating across the wider software organization. Operating in a fast-paced environment, the team plays a critical role in ensuring reliability, performance, and maintainability across the ML software stack, helping to deliver robust and high-quality products to customers. Responsibilities and Duties Design, implement, and maintain robust test infrastructure and automation for a complex ML software stack. Architect and evolve test frameworks and tooling with a focus on scalability, maintainability, and developer experience. Build and maintain CI/CD pipelines targeting simulators, emulators (e.g. QEMU), and physical hardware. Create representative ML workloads and gain insights from their execution. (Numerical accuracy, performance analysis and benchmarking). Work closely with all Software development teams, supporting a culture of quality, security and maintainability. Review code and designs, setting a high bar for software engineering best practices. Mentor and support junior engineers, helping raise the overall technical capability of the team. Evaluate existing test strategies and infrastructure, identifying gaps and driving improvements aligned with team and organizational goals. Candidate Profile Essential: Experience in production-quality software engineering roles. Strong software design and architecture skills, with experience working on large or complex systems. Strong proficiency in Python, including experience building and maintaining production codebases. Solid experience with CI/CD systems and automated testing (preferably GitHub-based workflows). Experience working in Linux environments. Familiarity with C or C++, with the ability to read, debug, and reason about low-level code when needed. Proven ability to mentor junior engineers and influence engineering practices within a team. Strong problem-solving skills and a proactive, self-directed approach to work. Bachelor/Master's/PhD or equivalent experience in Computer Science, Maths, Machine Learning, Data Science, or related field. Desirable Exposure to machine learning frameworks such as PyTorch, JAX, Triton, TensorFlow Experience with distributed workload management systems such as Kubernetes, VLLM, Keras or MLOps pipelines Experience working with hardware simulators or emulators (e.g. QEMU). Experience developing for or working with FPGA-based systems. Experience with people management or mentoring Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. Applicants for this position must hold the right to work in the UK. Unfortunately at this time, we are unable to provide visa sponsorship or support for visa applications
Graphcore
About us We are looking for a disciplined and dynamic Systems Engineer with focus on server CPU based system to join our growing compute rack validation team. Candidate we are seeking should have demonstrated work-experience in leading server rack and blade hardware systems deployment, hardware installation, and inventory management activities in the Austin, TX area. As a diligent leader in Systems Engineering, you will drive multiple aspects of post-silicon validation throughout the life cycle of the program. In this high visibility position, you will be part of a technical team chartered to innovate and improve system bring-up and enablement capabilities, as well as silicon and system validation to deliver the highest quality, industry leading technologies to market. Your technical leadership skills, systems engineering and hardware bring-up, validation and debug expertise will be necessary towards product development, definition, root cause and resolution. Your agility and collaborative approach will be essential to work within System Validation & other engineering teams (System Architects, SoC and Rack FW etc). The ideal candidate will be driving key areas around at-scale system validation including ARM based server and rack level systems bring-up (nodes and rack level systems). Candidate will be immersed in challenging system enablement work, ramp-up post-silicon capabilities in engineering lab environments, validation tests execution/triage. The candidate will be leading contributor towards state-of-the-art HW bring-up and lab capabilities for Grapchore’s system engineering. The candidate should be able to work in a global environment while maintaining a synergetic culture. Primary Responsibilities: Install, configure, commission (and decommission if needed) blade servers, chassis, switches, and supporting infrastructure. Lead rack and stack activities, including mounting equipment, cable management, and labelling. Execute hardware upgrades, replacements, and troubleshooting of server and network components. Maintain accurate asset records within DCIM platforms and inventory management systems. Conduct physical audits and reconcile inventory discrepancies. Track hardware movements, deployments, and decommissions through established change management processes. Document installation procedures, rack layouts, cabling diagrams, and inventory updates. Support data center migration, expansion, and refresh projects. Collaborate with engineering, operations, logistics, and project management teams. Adhere to all data center safety, security, and operational standards. Develop, setup and scale key methodologies for at-scale test execution, lab HW and system SW capabilities as well as system visibilities and debug tools necessary for successful system (HW/SW/FW) bring-up and system validation at blade and rack level for AI compute rack. Ability to work independently in a production ready environment, and a commitment tomaintaining accurate inventory and asset records. Triage issues found during server rack validation bring-up, Post-Silicon Validation, and production phases of the program. Ensure issues are solved on time with quality. Lead test execution of key domains within AI compute solutions like CPU, GPU, memory, HBM, IO etc. Drive technical innovation to improve capabilities across system validation, including tools, script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives. Qualifications: Strong analytical/problem-solving skills and pronounced attention to details Experience in Blade server installation and maintenance (Cisco UCS, HPE Synergy, Dell MX, or similar). Rack and stack deployments in enterprise or hyperscale environments. Copper and fiber cabling installation and management. DCIM and asset management platforms. Strong understanding of server, storage, and networking hardware. Experience performing inventory audits and maintaining asset accuracy. Ability to read rack elevation diagrams, cabling schematics, and deployment documentation. Familiarity with ticketing and change management systems. Exposure to Linux (ubuntu) OS bootable images and system firmware basics for image building, provisioning and firmware flashing. Exposure to automation testing, to enable execution of hardware acceptance tests, best-known-config testing etc. Exposure to python script development and execution. Proven experience in understanding, defining and enabling storage (storage rack), networking capabilities (network rack, DNS, DHCP etc) in a lab environment to help add end-to-end validation and debug capabilities for rack and blade validation. Excellent communication and coordination skills. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Technical leadership: capable of championing new tools, methods, and capabilities to drive platform validation improvements in schedule, quality, or coverage. Experience working with data center technical staff, 3rd party vendors, ODMs etc throughout the life cycle of server system product development. Must be a self-starter, and able to independently drive tasks to completion Preferred Qualifications: Masters or PhD in Electrical Engineering, Computer Engineering or a related field. 10+ years of work experience demonstrating working on complex systems engineering challenges to validate and debug HW-FW-SW challenges in a server compute rack or data center blade environment. Experience designing and deploying modern AI/ML rack scale systems Knowledge of industry standards and best practices for hardware development Familiarity with emerging technologies in AI and Data Center infrastructure. Comfortable meeting, engaging and collaborating with ODM partners and staffing vendors across the globe. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
We are looking for a disciplined and dynamic, Lead System Engineer – compute blade and rack Validation to join our growing compute rack validation team. As a diligent leader in Systems Engineering, you will drive multiple aspects of validation throughout the life cycle of the program. In this high visibility position, you will be part of a leading team to innovate and improve system bring-up and enablement abilities, as well as silicon and system validation to deliver the highest quality, industry leading technologies to market. Your technical leadership skills, validation and debug expertise will be necessary towards product development, definition, root cause and resolution. Your agility and collaborative approach will be essential to work within System Validation & other engineering teams (System Architects, SoC and Rack FW etc). The technical leader will be driving keys areas of system validation including leading first silicon & system bring-up (nodes and rack level systems) - rack level systems and blades will be based of ARM server architecture. Candidate will be immersed in challenging system enablement work, system validation (end-to-end) methodology, tests development and execution as well as triage/debug of critical issues to meet critical program milestones at POR quality. The candidate will also be a key contributor to state-of-the-art HW and lab capabilities for Grapchore’s system engineering. The candidate should be able to work in a global environment while maintaining a synergetic culture. Primary Responsibilities: Lead the systemenablement (including first silicon and other FW components) to ensure system capabilities are brought up as per plan of record and system architecture spec. Drive organization wide methodology for Firmware integration and best known configuration (HW/FW/SW) usage model by leading the release of deployment ready solutions. Develop key methodologies, lab HW and system SW capabilitiesas well as system visibilities and debug tools necessary for successful system (HW/SW/FW) bring-up and system validation at blade and rack level for AI compute rack. Triageissues found during server rack validation bring-up, Post-Silicon Validation, and production phases of the program. Ensure issues are solved on time with quality. Develop and own test plans,lead test case development and execution of key domains within AI compute solutions like CPU, GPU, memory, HBM, IO etc. Drive technical innovation to improve capabilities acrosssystem validation, including tool, script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives. Qualifications: Strong analytical/problem-solving skills and pronounced attention to details Extensive experience in validation roles involvingfirst silicon and system bring up, OS, FW, Silicon, and HW Understanding of PC industry standardbuses and their software stack, such as PCIe, CXL. Proven experience in understanding,defining and enabling storage (storage rack), networking capabilities (network rack, DNS, DHCP etc) in a lab environment to help add end-to-end validation and debug capabilities for rack and blade validation. Strong knowledge ofARM CPU or X86 architecture, SoC design, memory, RAS & power management as well as HW/SW based tools, and revision control systems. Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, DeviceDrivers and System BIOS interactions. Excellent communication and coordination skills. Detailed oriented, highly organized, able to prioritize, and juggle multiple workstreams to tight deadlines. Technical leadership: capable of championing new tools, methods, and capabilities to drive platform validation improvements in schedule, quality, or coverage. Deep experience with Linux and Windows Operating Systems, Hypervisors (VMware, KVM, Hyper-V, etc.), and development and certification processes of these environments Experience in technical program management. A thorough understanding of datacenter industry technologies and their software stack. Must be a self-starter, and able to independently drive tasks to completion Preferred Qualifications: Mastersor PhD in Electrical Engineering, Computer Engineering or a related 14+ years of work experience demonstrating working on complex systems engineering challenges to validate and debug HW-FW-SW challenges in a server compute rack or data center blade environment. Experience designing and deploying modern AI/ML rack scale systems Knowledge of industry standards and best practices for hardwaredevelopment Familiarity with emerging technologies in AI andData Center Comfortable meeting,engaging and collaborating with ODM partners across the globe. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
Senior: PLN 260,400 - 352,200 Staff: PLN 350,700 - 474,400 Subject to alignment to the responsibilities and duties of the role - we currently have multiple positions available at both Senior and Staff level About Graphcore At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence Job Summary As a Senior Machine Learning Engineer in the Applied AI team at Graphcore, you will contribute to advancing AI technology by developing and optimising AI models tailored to our specialised hardware. You will work on large scale systems where performance is critical to the success of our projects. Working closely with the Software development and Research teams, you will play a critical role in identifying opportunities to innovate and differentiate Graphcore’s technology. We seek engineers with strong technical skills and an understanding of AI model implementation at scale, eager to make a tangible impact in this rapidly evolving field. The Team The Applied AI team’s role is to be proxies for our customers, we need to understand the latest AI models, applications, and software to ensure that Graphcore’s technology works seamlessly with the AI ecosystem and at scale. We build reference applications, contribute to key software libraries e.g. optimising kernels for efficiency on our hardware, and collaborate with the Research team to develop and publish novel ideas in domains such as efficient compute, model scaling and distributed training and inference of AI models for multiple modalities and applications. If you're excited about advancing the next generation of AI models on cutting-edge hardware, we’d love to hear from you! Responsibilities and Duties Implement latest machine learning models and optimise them for performance and accuracy, scaling to 1000s of accelerators. Test and evaluate new internal software releases, provide feedback to software engineering teams, make necessary code fixes, and conduct code reviews. Benchmark models and key ML techniques to identify performance bottlenecks and improve model efficiency. Design and conduct experiments on novel AI methods, implement them and evaluate results. Collaborate with Research, Software, and Product teams to define, build, and test Graphcore’s next generation of AI hardware. Engage with AI community and keep in touch with the latest developments in AI. Candidate Profile Essential: Bachelor/Master's/PhD or equivalent experience in Machine Learning, Computer Science, Maths, Data Science, or related field. Proficiency in deep learning frameworks like PyTorch/JAX. Strong Python or C++ software development skills Expertise in deep learning from model training to optimisation and evaluation. Capable of designing, executing and reporting from ML experiments. Developed deep understanding of performance bottlenecks and how to overcome them. Ability to move quickly in a dynamic environment Enjoy cross-functional work collaborating with other teams. Strong communicator - able to explain complex technical concepts to different audiences. Desirable: Experience in one or more of: MLOps for Kubernetes-based clusters Building production systems with large language models Efficient computing based on low-precision arithmetic. Experience writing C++/Triton/CUDA kernels for performance optimisation of ML models. Experience in distributed training or inference of ML models across 64+ accelerators. Familiarity with HPC systems and networking including Infiniband, NVLink, RoCE technologies. Have contributed to open-source projects or published research papers in relevant fields. Knowledge of cloud computing platforms. Keen to present, publish and deliver talks in the AI community. Benefits In addition to a competitive salary, Graphcore offers annual leave policy, medical and dental health plans, a gym card, and employee pension (matched up to 4%). We review our benefits on a yearly basis to ensure we offer a valuable and rewarding benefits programme to our employees. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. Job Overview: Graphcore is seeking a Principal Engineer, Power Engineering to aid in defining the architecture of the power delivery components from grid to chip. You will work closely with multiple cross-functional teams, including hardware engineers, firmware developers, and data center operations, to ensure the infrastructure we build meets customer requirements as well as attaining standards of performance, reliability, and scalability. This role will be based in Austin or San Jose and could potentially be performed onsite or remotely within the US. Responsibilities: Provide thought leadership, planning, and design for power delivery from data center power drop through delivery to systems & chips Establish power roadmap. Work with vendors to ensure their planned future technologies are pulled into our system engineering roadmap AND ensure that our (system engineering) required technological innovation is being driven into their (power vendor) roadmap. Work to improve reliability and efficiency of power engineering component over time. Rack-level power components. Competency with specification of hardware and firmware for rack-level power shelves. Competency with design for resiliency. Set power policies in the data center for: power buffer/oversubscription, scheduling of jobs based on power, and monitoring (power quality faults) / accommodation faults. Resolve telemetry and data needed to support power policy algorithms. Ensure robustness of IT power in the presence of grid disturbances and make sure that IT power loads are compatible with grid power requirements (“good grid power citizen”) Board and system-level power regulation components. Understand and able to apply current VRM, TLDR, and POL technologies. Help to develop new technologies to increase efficiency. Understand manufacturing capabilities and limitations of new technology. Drive Provide guidance to the power equipment manufacturers, ODM and engineering teams on the required testing and validation procedures for power hardware and firmware components. Develop and test hardware prototypes as needed to support the exploration and validation of new concepts in power delivery. Tackle and resolve sophisticated power hardware and firmware issues as needed. Ensure compliance with industry standards and regulations. Required Skills and Experience : Bachelor’s or Master’s or PhD degree in Electrical Engineering with a specialized knowledge of Power Engineering. demonstrated ability in power system and delivery architecture, design, and development. Experience with rack-level hardware design, including servers, storage, networking, and power distribution. Proficiency in power hardware and firmware development and debugging. Excellent problem-solving and analytical skills. Strong communication and teamwork skills. Ability to work in a fast-paced, multifaceted environment. "Nice to Have" Skills and Experience: Familiarity with new technologies in AI and data center infrastructure. Comfortable meeting with and engaging directly with customers (internal and external) during requirements gathering and solution development Benefits In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About Graphcore At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary As a research engineer at Graphcore, you will contribute to the advancement of AI research, investigating new ideas that push the limits on important AI/ML problems. Specialised hardware has been the key driver of the progress of AI over the last decade, and we believe that hardware-aware AI algorithms and AI-aware hardware developments will continue to be critical to advancing this exciting field. We are therefore looking for individuals who combine strong machine learning experience with practical engineering skills to deliver impactful AI research. We are seeking AI researchers with strong software engineering experience, particularly in lower-level programming and performance optimisation for hardware efficiency. Our research spans a broad range of topics, including efficient training and inference, world models, life sciences, reinforcement learning, and beyond. You will work closely with researchers to generate ideas and translate them into scalable implementations, contributing to publications and projects that help to steer the future of AI hardware. The Team Graphcore Research participates in both fundamental and applied research, to characterise the computational requirements of machine intelligence and to demonstrate how hardware can drive the next generation of innovative AI models. We publish at leading AI/ML conferences (NeurIPS, ICML, ICLR) as well as specialist workshops, and collaborate with other research teams and organisations across the world. We pride ourselves on being a supportive and collaborative team, where we organise around our individual research interests to solve problems together in domains such as efficient compute, model scaling and distributed training and inference of AI models for multiple modalities and applications, including for sequence- and graph-based data. We’re based across London, Cambridge and Bristol, with projects and discussions that involve all our locations. Perhaps the best way to get an idea of what we’re all about is to read one of our papers or an article on our blog. If you’re excited to work at the cutting edge of AI supported by new hardware and want to develop your skills in this area, we’d love to hear from you! Responsibilities and Duties Generate AI/ML ideas, design experiments, implement them & evaluate results. Prepare, submit & present your work to AI conferences and workshops. Provide technical insight to internal teams by designing experiments and delivering clear, actionable reports. Collaborate with researchers, silicon and software engineers at Graphcore to help define, build and test Graphcore’s next generation of AI hardware. About you: Essential: Master’s, PhD or equivalent experience in a technical discipline (e.g., Maths, Statistics, Computer Science, Physics, Chemistry). Python programming in a modern deep learning framework, e.g. PyTorch or JAX. Familiar with deep learning fundamentals: models, optimisation, evaluation and scaling. Capable of designing, executing and reporting from ML experiments. Lower-level programming for hardware efficiency, e.g. C++/CUDA/Triton. Practical familiarity with hardware capabilities for deep learning – threads, caches, vector & matrix engines, data dependencies, bus widths and throttling. Practical familiarity with software stacks for deep learning – compilation, kernel fusion, XLA/ATen ops, streams, and asynchronous execution Desirable: Mathematics skills to support the above: calculus, probability theory and linear algebra. Experience submitting papers to international scientific conferences or workshops. Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. Applicants for this position must hold the right to work in the UK. Unfortunately at this time, we are unable to provide visa sponsorship or support for visa applications
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a Technical Program Manager with physical design expertise to drive execution of our industry-leading AI/ML and CPU processor projects. You'll lead cross-functional teams, manage complex schedules across multiple chiplets, and serve as the primary interface between internal teams and external partners. If you combine technical depth in physical design with exceptional program management skills and want to shape the delivery of next-generation AI silicon, join our team. This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Ft. Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned program manager with hands-on physical design background and deep understanding of semiconductor development. An exceptional communicator who builds strong relationships with both internal teams and external clients. Detail-oriented and well-organized, with proven ability to manage multiple complex projects simultaneously. A technical leader who can translate between engineering details and strategic program objectives. What We Need BS/MS/PhD in EE/ECE/CE/CS with 5+ years of technical program management in the semiconductor industry. Experience with synthesis, place and route flows, timing analysis, EM/IR, and physical verification. Track record of successfully managing design services partners and client relationships. Strong ability to create and drive schedules while ensuring cross-team alignment on priorities and dependencies. What You Will Learn How to orchestrate complex physical design projects for cutting-edge AI/ML and CPU architectures. Advanced techniques for managing multi-chiplet programs and coordinating with world-class engineering teams. Best practices for balancing technical depth with strategic program execution in a fast-paced environment. Direct influence on project success through ownership of schedule and milestone deliverables. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin,TX or Santa Clara,CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-standard tools (Innovus, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python). Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling). Experience driving physical design requirements from early architecture through final signoff. Experience in power grid design and EMIR is preferred What You Will Learn How to implement cutting-edge AI accelerators and high-performance CPUs on the most advanced process nodes. Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures. End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams. Direct impact on products that are redefining the landscape of AI and high-performance computing. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-standard tools (Innovus, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python). Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling). Experience driving physical design requirements from early architecture through final signoff. What You Will Learn How to implement cutting-edge AI accelerators and high-performance CPUs on the most advanced process nodes. Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures. End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams. Direct impact on products that are redefining the landscape of AI and high-performance computing. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance. The ideal candidate has a strong background in DevOps, workload porting, or application enablement. While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale. This role is remote, based in the United States or Australia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware. Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier. A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through strategic IT and DevOps enablement. Collaborative & Cross-Functional: You enjoy acting as the "technical glue" between IT, DevOps, and AI teams, coordinating complex efforts across boundaries to ensure seamless workload transitions. Architecture Agnostic: You are a systems thinker who understands how to bridge the gap between infrastructure and core silicon engineering. What We Need Education: BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field. Workload Expertise: Extensive experience in workload porting, DevOps engineering, or application enablement. Systems Fluency: Strong familiarity with CPU architectures and systems design, with a proven track record of troubleshooting and optimizing performance across new architectures. Leadership Qualities: Ability to coordinate across multiple technical teams and the potential to mentor or grow a small engineering pod. Execution Focus: A mindset geared toward technical delivery and methodology development rather than broad community networking. What You Will Learn Gain deep expertise in bleeding-edge RISC-V system software across server and AI-accelerated environments. Directly influence an upcoming project, a high-visibility initiative shaping the future of our internal compute infrastructure. Work at the intersection of AI/ML workloads and hardware/software co-design. Shape the technical roadmap for how the industry adopts RISC-V for high-performance compute. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the unit specification, RTL design, and unit verification. This role is Remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Key Responsibilities: RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure. RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA. AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process. Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team. Qualifications: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V. Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…) Deep understanding of CPU microarchitecture and PPA trade-off. Basic understanding of RISC-V Architecture including V-extension is preferred. Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL. Excellent problem-solving abilities and analytical skills. Strong communication skills, with the ability to convey complex technical concepts to diverse audiences. Ability to work collaboratively in a team-oriented environment and across multiple disciplines. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building next-generation AI systems that push the boundaries of model training, inference, and large-scale distributed compute. The ML Models team sits at the intersection of cutting-edge AI research and high-performance hardware, bringing state-of-the-art machine learning models to life on Tenstorrent’s custom AI accelerators. From training large language models to optimizing inference performance at scale, this team works across the full stack to turn breakthrough research into production-ready AI systems. If you are passionate about advancing the frontier of AI research, inference and training optimizations, this is an opportunity to shape how future AI models are developed and deployed. This role is hybrid, based out of Toronto, ON and Boston, MA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong Python and PyTorch experience developing and training deep learning models. Deep understanding of ML architectures, LLM training, and inference optimization. Hands-on experience training large-scale machine learning models. 4+ years of industry and/or academic experience in ML research and LLM development. PhD, published research, or experience with speculative decoding is highly valued. What We Need Lead research and development efforts focused on LLM training and inference optimization. Train, evaluate, and optimize state-of-the-art AI models on Tenstorrent hardware. Improve performance through techniques such as speculative decoding, quantization, kernel fusion, flash attention, and distributed training. Investigate system bottlenecks and collaborate cross-functionally to drive performance improvements. Translate cutting-edge ML research into scalable, production-ready solutions. What You Will Learn How to optimize AI models on custom AI accelerators from application to silicon. How large-scale ML systems are deployed, tuned, and scaled in production. How hardware, compiler, kernel, and ML teams collaborate to maximize performance. The challenges and tradeoffs of scaling modern AI workloads across custom hardware. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. This role is remote based out of the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are You have a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science, along with 10+ years of relevant DFT experience. You have hands-on experience with industry-standard DFT tools such as Synopsys and Siemens, as well as scripting in TCL and Python. You bring expertise in DFT planning, SoC-level silicon debug, formal verification, and signoff of inserted DFT logic. You are a strong cross-functional collaborator who can assess risk, communicate resource needs, and deliver in a complex technical environment. What we need Build and execute chip-level DFT strategies for high-speed CPU core designs and multi-chiplet System-in-Package programs. Implement and verify DFT features including scan chains, memory BIST, and JTAG to support manufacturing test and silicon debug. Partner with RTL, physical design, and verification teams to ensure testability throughout the design flow. Script, automate, and analyze DFT flows using industry-standard EDA tools, including ATPG and fault coverage reporting. What you will learn How to develop DFT strategies for advanced multi-chiplet and System-in-Package designs. How Tenstorrent approaches testability, silicon bring-up, and manufacturing readiness for high-performance CPU programs. How to work across global teams and external stakeholders on complex silicon development efforts. How to scale DFT execution through automation, deeper cross-functional collaboration, and continuous IP improvement. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You’ll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes. This role is remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An experienced physical design engineer with at least 10 years of relevant experience, who thrives in complex, multi-stakeholder projects. Detail-driven, with a strong sense of ownership from synthesis through design closure. Comfortable working at advanced nodes (3nm and below) and multi-GHz designs. A collaborative team player who enjoys mentoring others and influencing methodology. Clear communicator who can balance technical depth with schedule and resource constraints. What We Need Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science. 10+ years of industry experience in physical design for CPU, or GPU products. Strong hands-on experience with Synopsys and/or Cadence tools across synthesis, P&R, and closure. Proven expertise in timing closure, ECO flows, and PV convergence at block and chip level. Proficiency in scripting (TCL required; Python or similar strongly preferred) and strong English communication skills. What You Will Learn How large-scale chiplet-based systems are architected, implemented, and integrated into SiP solutions. Best practices for achieving timing and power convergence on advanced silicon technologies. How physical design decisions impact system-level performance and scalability. Effective collaboration across global teams and external partners. How Tenstorrent evolves and standardizes physical design methodologies across projects. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an experienced Analog Design Engineer to develop cutting-edge die-to-die chiplet PHY IP solutions that power the future of AI computing. You'll work at the forefront of deep sub-micron technologies, collaborating with circuit architects and cross-functional teams to push the boundaries of analog/mixed-signal design. If you have a proven track record of delivering production-quality silicon and want to innovate at the heart of next-generation interconnects, join our team. This role is remote, based out of any in North America. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are A Analog/Mixed-Signal Design Engineer to develop die-to-die chiplet PHY IP, including PLLs and key analog/mixed-signal blocks in deep sub-micron FinFET technologies. A hands-on owner for the full lifecycle: design, verification, layout interaction, tape-out, and silicon bring-up to production quality. A strong cross-functional partner who can work with architecture, analog, digital, verification, layout, and software teams to integrate and optimize AMS IP. What we need 10+ years of analog/mixed-signal IC design experience in FinFET, including PLL/AMS design, with an MSEE/PhD or equivalent background. Strong track record in production tape-outs, silicon bring-up/testing, and hands-on use of industry-standard EDA tools with close layout collaboration. Deep experience in high-speed datacomm/SerDes and die-to-die PHY design, including Tx/Rx, DDR, PCIe, and USB PHY components. Collaborative, self-driven engineer with expertise across key circuits such as bias generators, amplifiers, LDOs, ADCs/DACs, oscillators, switched-cap circuits, plus familiarity with high-speed digital and equalization techniques like CTLE, DFE, and de-emphasis. What you will learn How to push the limits of die-to-die chiplet PHY IP in advanced FinFET nodes, from architecture through high-volume production. How to co-optimize analog, digital, and layout to hit aggressive performance, power, and area targets in complex SoCs. Deeper expertise in high-speed I/O and PHY architectures, plus practical methodologies for scalable, reusable AMS IP across multiple products. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
ASML
R&D engineering for High-NA Twinscan EUV systems. Sub-nanometer mirror positioning, laser-produced plasma (LPP) light sources, and wafer stage control dynamics.
imec
IMEC Belgium research on sub-1nm GAA Nanosheet transistors, High-NA EUV lithography resists, 3D wafer bonding, and backside power delivery network (BSPDN).
Verified Organization
Jet Propulsion Laboratory (JPL) research position on space-grade radiation-tolerant RISC-V microarchitectures, triple modular redundancy (TMR), and CubeSat payload electronics.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Advanced Packaging Process Engineer with experience in 2.5D and 3D chiplet packaging to join Tenstorrent’s Packaging team. You will drive advanced package technology and reliability in close partnership with foundries and OSATs, helping push performance and manufacturability for next‑generation AI/ML products. This role is hybrid, based out of Santa Clara, CA or Taipei City, TW. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are Advanced packaging engineer with hands-on 2.5D/3D experience (CoWoS-R/L, FOCoS, EMIB, FCBGA, organic substrates, silicon interposers, embedded Si/eCB, micro-bumps, BGAs). Strong in reliability and failure analysis for advanced packaging, including qualification, root cause analysis, and corrective actions. Deep understanding of process flows and materials (polyimide, ABF, core, underfill, mold compound) and their interactions (warpage, stress, delamination, mechanical risk). Proven track record working with foundries/OSATs on NPI, design rules, excursions, yield/cost optimization, and production ramp, with clear communication and cross-functional collaboration. What we need Own advanced package technology implementation for 2.5D/3D chiplet products, including technology choices, process integration, and manufacturability. Act as primary technical interface to foundries/OSATs: align capabilities and design rules, manage excursions, drive yield, define/track test vehicles, and coordinate FA. Partner with design, reliability, and architecture teams to evaluate tradeoffs (bump pitch, stack-ups, embedded Si, etc.) and lead test vehicle planning to meet program needs. MS/PhD in a relevant field (Materials, Mechanical, Electrical, Physics, or related) and 5+ years in advanced packaging for high-performance semiconductors from NPI through production (2.5D/3D flows such as CoWoS, FOCoS, EMIB, FCBGA or equivalent). What you will learn Deeper exposure to leading-edge 2.5D/3D packaging for high-performance AI/ML and chiplet-based architectures. How to balance performance-driven architecture with mechanical and reliability constraints to make robust package technology decisions. Ways to use AI- and automation-driven methods to accelerate risk assessment, qualification planning, and technical documentation. Best practices for building strategic OSAT and foundry partnerships that enable new capabilities while scaling reliable high-volume production. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Implementation of DFT features into RTL using verilog. Understanding of DFT Architectures and micro-architectures. ATPG and test coverage analysis using industry standard tools. JTAG, Scan Compression, and ASST implementation. Gate level simulation using Synopsys VCS and Verdi. Support silicon bring-up and debug. MBIST planning, implementation, and verification. Support Test Engineering on planning, patterns, and debug. Develop efficient DFx flows and methodology compatible with front end and physical design flows Experience & Qualifications: BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques. DFx experience implementing in finFET technologies. Experience with industry standard ATPG and DFx insertion CAD tools. Familiarity with SystemVerilog and UVM. Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors. Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling. Good understanding of high-performance, low-power design fundamentals. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. Exposure to post-silicon testing and tester pattern debug are major assets. Experience with Fault Campaigns a plus. Strong problem solving and debug skills across various levels of design hierarchies. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a senior physical design engineer to join Tenstorrent’s AIDC Yayoi project, driving chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a cutting-edge system-in-package environment. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or computer science, with extensive experience (typically 10+ years) in SoC/ASIC/GPU/CPU physical design on taped-out designs. You are highly skilled with industry-standard tools (e.g., Synopsys/Cadence) and physical verification, and comfortable scripting in TCL and at least one other language (e.g., Python). You are a strong collaborator who can guide and mentor junior engineers, communicate clearly with global stakeholders, and navigate complex technical trade-offs to drive designs to closure. You are organized and data-driven, able to build implementation plans, monitor PPA and schedule metrics, communicate resource needs, and proactively identify and manage risks. What We Need Lead chiplet and chip-top implementation for a high-profile, multi-chiplet System-in-Package project and place and route for high-speed CPU core designs in advanced nodes (5nm and below). Own chip-top floorplanning and integration: BUS and fabric planning, bump and IO placement, and hierarchical top/bottom floorplanning to achieve timing and PPA closure at chip level. Drive full physical verification and convergence, electrical rules, DRC/LVS, noise, and electromigration checks Take ownership of chip-level synthesis, BUS and bump planning, SoC floorplanning, and chip-top PV and EMIR, while providing technical leadership and mentoring to junior team members. What You Will Learn Deep expertise in system-in-package design and multi-chiplet integration, working hands-on project with complex chip-top interfaces and constraints. Best practices for high-frequency, advanced-node (5nm and below) CPU design implementation, including cutting-edge timing closure, EMIR, and sign-off methodologies. How to operate in a highly collaborative global environment, partnering daily with Tenstorrent experts and leaders across Japan, the USA, and other regions, as well as external stakeholders. Advanced strategies for scaling physical design flows, improving reproducibility of convergence, and optimizing project PPA and schedule across multiple tapeouts. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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