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Graphcore
Staff Embedded SW/FW Engineer (Bringup) Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon bringup sequences and test in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy configuration sequences and validation tests on first silicon and debug them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Candidate Profile Essential: Strong experience in Bare metal / embedded C/C++ Good knowledge of digital ASICs. Be highly motivated, a self starter, and a team player Ability to work across teams and programming languages to find root causes of deep and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Python, Linux Excellent communication skills and the ability to collaborate with others to solve problems. Excellent problem-solving, analytical & diagnostic skills Desirable: Driver level experience with one or more of the following is highly desirable: PCIe Ethernet Memory technologies (LPDDR, DDR, HBM, …) Other peripherals such as I2C, I3C, SPI, … Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable. Experience of Arm CPUs, System IP and debug tools. Experience of AMBA protocols. Understanding of ML applications and their workloads. Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support Benefits: In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About the job Own the reliability strategy behind advanced AI silicon built for datacenter scale. Graphcore is expanding the hardware platforms that will power the next generation of AI compute. As Senior Semiconductor Reliability Engineer, you will lead reliability strategy across advanced silicon nodes and packaging technologies. You will shape reliability from technology selection and design enablement through bring-up, qualification and manufacturing. Your work will help complex, high-performance devices move from ambitious design into robust production. You will assess risk, guide sign-off, lead qualification and drive failure analysis across silicon, interconnect and package technologies. This is a rare role at the centre of device physics, design, packaging and manufacturing. The team and culture You will work across silicon, packaging, manufacturing and quality, connecting technical detail with product-level decisions. Work moves through direct ownership, clear evidence and fast escalation when risks need attention. Decisions are grounded in data, modelling, qualification results and open technical debate. You will be expected to speak up, challenge assumptions and turn complex findings into clear next steps. This is a role for someone who thinks beyond individual tests. You will help build stronger reliability methods and mentor others as Graphcore scales advanced AI hardware platforms. What we’re looking for · Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, or a related field · Strong semiconductor reliability experience across silicon, BEOL, interconnect or advanced package technologies · Deep understanding of mechanisms such as EM, TDDB, BTI and HCI · Hands-on experience with HTOL, thermal cycling, thermal shock, reflow testing and JEDEC reliability standards · Ability to use X-ray and CSAM analysis to diagnose package defects and support root-cause analysis · Strong technical judgement, communication skills and ownership across foundries, OSATs, labs and internal teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how your background makes you a strong candidate. Benefits · Flexible working: Balance your work and personal life with greater flexibility · Generous leave: Take time to rest, recharge and enjoy life outside of work · Retirement planning support: Up to 5% matched pension · Phantom equity: Share in Graphcore’s success · Workplace experience: Enjoy thoughtfully designed office spaces for collaboration, with free food and an on-site barista to support your day · Peace of mind protection: Income protection and life assurance to provide financial security for you and your loved ones · Flexible benefits: Tailor your benefits package with a choice of additional options, including private medical insurance and dental cover · Optional benefits: Dental cover, health cash plan, private medical insurance, cycle to work scheme, give as you earn We welcome people from all backgrounds and experiences and are committed to building an inclusive environment where everyone can do their best work. We’re an equal opportunity employer and recognise that everyone brings different strengths and perspectives. If you need any adjustments during the interview process, just let us know - we’re happy to support you. Sponsorship We offer sponsorship for this role. Join the Team at Graphcore Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore brings together deep expertise to solve complex problems and deliver meaningful progress in AI compute. If you want to shape the reliability foundations of advanced AI silicon at Graphcore, we’d love to hear from you. Apply now to be part of the journey.
Graphcore
Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties Execute validation and bring-up activities for DDR and HBM memory subsystems Verify memory bring-up software, firmware and scripts against defined project requirements Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities Analyse system logs, validation data and characterization results to identify failures and performance issues Perform PHY characterization and analog-level analysis during stress testing and validation activities Develop and execute functional, stress, performance and corner-case validation tests Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation Characterize memory bandwidth, latency, training behaviour and subsystem stability across operating conditions Develop Python-based automation, test infrastructure and reporting tools to improve validation efficiency Collaborate with architecture, RTL, firmware and platform teams to investigate and resolve technical issues Contribute to memory subsystem debug activities spanning silicon, firmware, board and system domains Support development of validation methodologies, debug procedures and reporting frameworks Contribute to continuous improvement of validation infrastructure and engineering processes Support silicon characterization, production readiness and qualification activities Document validation results and communicate findings to the wider engineering team Candidate Profile Essential Strong experience validating DDR, LPDDR, HBM or related DRAM technologies Deep understanding of DRAM architecture, memory subsystem operation and memory controller functionality Experience with firmware, BIOS and Embedded C development Strong programming skills in C and Python Hands-on experience using laboratory equipment including oscilloscopes and related measurement instrumentation Experience interfacing with low-speed peripherals including GPIO, SPI, I2C and UART/serial interfaces Experience performing functional testing and signal measurements including voltage, frequency and timing analysis Strong knowledge of embedded systems and microcontroller-based platforms Hands-on experience with board bring-up and hardware validation activities Experience debugging complex hardware, firmware and system-level issues Experience performing silicon characterization and analysing validation results Strong analytical, diagnostic and problem-solving skills Excellent communication and collaboration skills with the ability to work effectively across multidisciplinary teams Desirable Experience with memory IP bring-up environments, firmware or validation software Experience with DDR or HBM PHY behaviour, memory controller architectures, training algorithms and calibration flows Knowledge of memory subsystem performance analysis and workload characterization Experience with memory margining, stress testing and reliability validation Familiarity with JTAG, trace infrastructure and low-level debug tools Experience with high-performance compute, AI accelerator or data center systems Understanding of signal integrity and power integrity considerations in high-speed memory systems Experience developing validation automation frameworks and regression environments Experience supporting first-silicon bring-up and production readiness activities
Graphcore
About Graphcore At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary We are looking for an experienced Silicon Test Engineer to join our Product Test and Diagnosis Department (PTD). This is a pivotal role and will involve building a team of engineers to develop System Level Test (SLT) capability within the company. Working closely with a cross-functional team you will implement SLT tests for a family of next generation AI Processors. The ideal candidate should have a focus on quality and demonstrate a good understanding of the importance of production test on the success of a product. They will have a proven Functional Test or ATE Test Engineering background, and will have a pragmatic, hands-on and flexible approach to a fast-changing environment. The Team The Product Test and Diagnostics team’s role is to detect and manage hardware defects that arise from the manufacture and use of our products. This covers chips, boards and finished systems and takes place both in the manufacturing sites and in the field. Responsibilities and Duties Managing a team of engineers to implement SLT test solutions for a multi-die AI Processor product Working with the Silicon, Test and DFT teams to define manufacturing test solutions Working with key industry leaders to develop an SLT system capable of meeting the products needs Understanding of top, and board level DFT strategies within a 3D, multi-die product Understanding of implementation details for an Incoming Quality Inspection (IQC) stage, and the inter-department complexities Defining test fixtures for SLT Test Solutions: Structural and functional test equipment, interface PCBs, sockets, cooling systems, etc Writing Production, Engineering and Characterisation Test Programs on Advanced SLT platforms Working with other departments to balance test coverage and fault detection across all test stages in the flow; ATE, board, blade, and in-field test Correlation to bench measurements Transferring test solutions to the offshore vendors, as part of an NPI release Work collaboratively with other engineering teams to ensure successful silicon, and board bring-up and help identify any silicon failures to enhance yield learning and improvement Candidate Profile Essential: A pragmatic approach, the ability to improvise, pitch in, and get the job done Experience in production test of large digital devices Very good knowledge of digital integrated circuits and advanced test techniques Very good understanding of DFT components such as (i)JTAG (IEEE 1149.x), BIST, MBIST, etc Understanding of functional test of complex systems Experience in transferring to volume manufacture to OSATs and Contract Manufacturers Ability to work within high pressure cross-department and cross-company teams Ability to mentor junior members of the team Strong scripting and debugging skills using programming languages like Python, TCL, Perl, Shell etc Degree level qualifications in electronics or a related field Good communication skills Desirable Proven competence on SLT testers Experience of thermal control of high-power devices in a production environment. Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About the job Help shape the first moments of life for the next generation of AI processors. You'll lead the bring-up and characterisation of Graphcore's silicon devices and system platforms. Your work will ensure products perform reliably before they reach customers. You'll build and lead a team that develops characterisation plans, automates testing, and analyses results across silicon and system platforms. You'll work closely with architecture, silicon, hardware, operations and product teams to solve complex technical challenges. This is a hands-on technical leadership role with the opportunity to influence product design, shape new capabilities, and build a team from the ground up. The team and culture You'll join a newly formed team within Manufacturing Operations and help define how bring-up and characterisation is delivered at Graphcore. Your decisions will shape the team's direction as it grows. The team works closely with colleagues across Bristol, Cambridge and Taiwan. Success comes from solving problems together, sharing data, and making informed engineering decisions. You'll be trusted to take ownership, remove blockers, and improve how work is done. We value people who speak up, challenge assumptions, and turn ideas into practical solutions. What we're looking for Essential Proven track record of delivering technical outcomes as an individual contributor, manager, or project manager, with strong communication and stakeholder management skills. Solid experience in silicon digital device design, bring-up, and characterisation, with a good understanding of silicon process technology and its impact on transistor- and system-level performance. Strong knowledge of high-performance processors, system-on-chip (SoC) architectures, and high-speed digital interfaces such as PCIe, Ethernet, and DDR. Experience with measurement automation, data analysis, and developing code or scripts to support automated testing and analysis workflows. Bachelor's degree (or equivalent practical experience), with a background understanding of ATE systems and their role in silicon characterisation. Desirable Knowledge of PCBA and system level technologies. Project management experience. Benefits Unlimited annual leave Up to 5% matched pension Phantom equity – share in Graphcore's success True flexibility in how and where you work Office spaces designed for collaboration Free food and an on-site barista Health cash plan Income protection Life assurance Along with other benefits you can choose from (private medical insurance, dental plan etc) Inclusion statement We welcome people from all backgrounds and experiences and are committed to building an inclusive environment where everyone can do their best work. We're an equal opportunity employer and recognise that everyone brings different strengths and perspectives. If you need any adjustments during the interview process, just let us know. We're happy to support you. Join the Team at Graphcore Graphcore is building the compute platform for the next generation of artificial intelligence. From advanced silicon to intelligent software, our technology is designed to unlock breakthroughs in AI and bring its benefits to every industry. As part of the SoftBank Group, we're backed by one of the world's most ambitious technology investors, working alongside companies shaping the future of AI. Together, we share a bold goal: to help enable artificial superintelligence and ensure it delivers meaningful impact at a global scale. At Graphcore, you'll work with people who are pushing the boundaries of what's possible. Our teams bring together AI researchers, chip designers, software engineers and systems experts from a wide range of backgrounds. It's an environment where we take on big challenges with curiosity and focus, move quickly and decisively, take real ownership of our work, and speak up to challenge ideas, stepping up to support each other and lead through action. If you want to build the systems that validate the next generation of AI hardware and lead a team making a measurable impact, we'd love to hear from you. Apply now to join Graphcore.
Graphcore
About the job Validate the power systems that keep advanced AI compute stable, efficient and ready for real product conditions. As a Validation and Debug Engineer, you will help prove Graphcore silicon and platforms work across demanding system conditions. You will build deep understanding of our devices, boards, power delivery and system behaviour. You will create and execute bring-up and validation plans for new hardware platforms. Your focus will include multi-phase SMPS, power delivery networks, voltage rails, sequencing, ripple, noise, efficiency and thermal performance. This is hands-on lab work with real ownership. You will investigate failures, analyse power integrity and turn complex findings into clear actions across hardware and firmware. The team and culture You will work with Architecture, Silicon Engineering, Hardware Engineering, Firmware, PCB design, power and signal integrity teams. Progress comes through measured evidence, practical judgement and clear debug reports. The team moves quickly because the problems are complex and close to the hardware. You will own bring-up activity, drive root cause analysis and keep issues moving across teams. Decisions are made close to the data. You will be expected to speak up, challenge assumptions and help teams choose the right corrective action. What we’re looking for · Strong hands-on hardware validation and debug experience, including board bring-up and subsystem debug · Experience validating multi-phase SMPS and power delivery networks for complex hardware platforms · Ability to debug PCB, power, signal integrity and interface issues through to root cause · Knowledge of voltage rail validation, sequencing, transient response, load regulation, ripple, noise and thermal behaviour · Confident use of lab instrumentation, including high-bandwidth oscilloscopes, logic analysers, electronic loads and power analysers · Ability to work independently, take responsibility and drive issue resolution across hardware and firmware teams While we have outlined a set of requirements, we value transferable skills and diverse experiences. If you meet most of our essential criteria, we encourage you to submit an application and showcase how your background makes you a strong candidate. Benefits · Flexible working: Balance your work and personal life with greater flexibility · Generous leave: Take time to rest, recharge and enjoy life outside of work · Retirement planning support: Up to 5% matched pension · Phantom equity: Share in Graphcore’s success · Workplace experience: Enjoy thoughtfully designed office spaces for collaboration, with free food and an on-site barista to support your day · Peace of mind protection: Income protection and life assurance to provide financial security for you and your loved ones · Flexible benefits: Tailor your benefits package with a choice of additional options, including private medical insurance and dental cover · Optional benefits: Dental cover, health cash plan, private medical insurance, cycle to work scheme, give as you earn We welcome people from all backgrounds and experiences and are committed to building an inclusive environment where everyone can do their best work. We’re an equal opportunity employer and recognise that everyone brings different strengths and perspectives. If you need any adjustments during the interview process, just let us know - we’re happy to support you. Sponsorship Applicants must have the legal right to work in the UK. Unfortunately, we are unable to provide visa sponsorship or support visa applications for this role. Join the Team at Graphcore Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore brings together deep expertise to solve complex problems and deliver meaningful progress in AI compute. If you want to validate the power foundations of next-generation AI compute, we’d love to hear from you. Apply now to join Graphcore.
Graphcore
Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are expending our labs in Bristol which will play a central role in Graphcore's work building the future of AI computing. We are looking for a Validation and Debug engineer to work with Architecture, Silicon Engineering, Hardware Engineering and the Firmware team to help create and execute the bring-up and debug of our cutting-edge system platforms. As such you will need to develop a detailed understanding of our silicon and platform products. Your role will be to create and execute Validation and Debug plans of our silicon devices and platforms in systems to show that they will operate correctly over all conditions in the final product. This Validation will also involve debugging of hardware and firmware. You will concentrate on mainly manual testing of systems in the lab with the aid of some automation. Responsibilities and Duties Perform Validation and Debug for new hardware platforms. Debug PCB, power, signal integrity, and interface issues. Validate and debug high-speed memory interfaces and slow speed interfaces LPDDR5-9600 memory interfaces SPI/I2C/I3C/UART Support LPDDR5-9600 initialization, training, timing optimization, margin analysis, and stability validation. Analyse DDR timing margins, signal integrity, eye diagrams, and training behaviour. Identify root causes and drive corrective actions across hardware and firmware domains. Create bring-up documentation, test procedures, and debug reports. Working closely with: PCB design engineers Power engineers Signal integrity engineers Embedded software teams Essential skills Hardware Debug LPDDR validation and tuning Signal integrity analysis DDR training and margin analysis Protocol-level debugging Root-cause analysis Low-level system integration An ability to work independently without daily oversight. Independently performs board bring-up and subsystem debug Drives issue resolution across teams. Use advanced lab instrumentation including: High-bandwidth oscilloscopes BERT systems VNA/TDR equipment Hands-on experience with: LPDDR5 memory subsystems LPDDR5 compliance testing Desirable skills: Knowledge of PCBA and system level technologies Ethernet validation PCIe Background knowledge of ATE systems and capabilities. You may not be directly involved with such testing. The ability to code or script automation and data analysis using appropriate coding languages such as Python, LabView and BASH. Benefits: In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
1418 Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. The Electrical Engineer will play a pivotal role in designing innovative hardware systems for AI/ML applications. We are seeking a motivated Electrical Engineer with 2–4 years of experience in schematic capture, PCB design, and server hardware development. This role includes close collaboration with multiple partners to drive designs from concept through mass production. The ideal candidate is comfortable working across organizational boundaries, ensuring design quality, manufacturability, and on-time delivery in a fast-paced environment. Responsibilities: Develop and maintain electrical schematics for various printed circuit assemblies Design and layout multilayer PCBs Work closely with partners to review designs, provide technical guidance, and ensure alignment with system requirements Drive design for manufacturability (DFM), design for assembly (DFA), and design for testability (DFT) Support server subsystem integration Participate in design reviews Support prototype builds, board bring-up, debugging, and validation Track and resolve design issues, including root cause analysis and corrective actions Ensure proper documentation, revision control, and engineering change management (ECO/ECN processes) Requirements: Bachelor’s degree in electrical engineering 2–4 years of experience in schematic capture and PCB design Proficiency with PCB design and schematic tools Strong understanding of analog and digital circuit design fundamentals Experience with multilayer PCB layout Experience with lab equipment (oscilloscope, multimeter, logic analyzer) Differentiators: Experience with server platforms or data center hardware Knowledge of power delivery network (PDN) design for high-power systems Familiarity with signal integrity and power integrity analysis tools Experience with compliance and validation (EMI/EMC, safety, regulatory) Exposure to global manufacturing environments and supply chain coordination Familiarity with PLM systems and change management workflows We welcome people of different backgrounds and experiences and are committed to building an inclusive work environment that makes Graphcore a great home for everyone. We are an equal opportunity employer and want to build a work environment where everyone is happy, productive and respectful so they can do their best work. If you have a disability or additional need that requires accommodation, just let us know. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an AI Processor IP Product Engineer to be the technical bridge between our cutting-edge AI processor technology and customer success. You'll guide customers through the integration of our advanced AI processors, RISC-V CPUs, and chiplet solutions into their SoCs, ensuring optimal performance and accelerated time-to-market. If you thrive in customer-facing roles and want to shape the deployment of revolutionary AI hardware across the industry, join our team. This role is hybrid, based out of Toronto, Canada or Vancouver, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A customer-focused engineer with deep technical expertise in ASIC design and IP integration. Experienced problem-solver who excels at debugging complex system-level issues and silicon bring-up. Strong communicator who builds trusted relationships while managing technical engagements across the support lifecycle. Passionate about enabling customer success and translating complex technical concepts into actionable guidance. What We Need 3-5 years in the semiconductor industry with a degree in EE or related field. Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL). Strong background in analog/digital design tools, silicon validation, and system-level debug. Proven track record in customer-facing engineering roles with excellent communication skills. What You Will Learn How to integrate state-of-the-art AI processors and chiplet architectures into diverse customer SoCs. Advanced debugging techniques spanning pre-silicon simulation to post-silicon validation. Strategies for influencing product roadmaps through direct customer feedback and technical insights. The full spectrum of IP productization—from technical documentation to customer training and support processes. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a Software Driver Developer to create reference drivers for our AI-IP in a reference system. You will also support our AI-IP customer optimizing our reference driver into our customer specific systems. This role is hybrid, based out of Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deep systems engineer with 7+ years of experience in device drivers or low-level systems programming. Strong proficiency in C and C++ with a solid understanding of hardware-software interfaces. Hands-on experience developing Linux kernel drivers, including kernel architecture, debugging, and kernel-space/user-space interactions. Experience developing drivers for high-speed I/O or interconnect technologies such as PCIe; PCIe driver development is strongly preferred. Familiar with user-mode and kernel-mode driver models and understands that Linux kernel driver development differs meaningfully from bare-metal or RTOS-based driver development. What We Need Design and evolve the driver layer that provides high-performance APIs for Tenstorrent devices. Develop and maintain user-mode and kernel-mode drivers for Tenstorrent hardware, including Linux kernel drivers for system integration. Define driver interfaces and specifications that enable the broader software stack to run across internal and third-party hardware. Collaborate with kernel and hardware teams to ensure efficient cross-layer design, performance, and PCIe-based device integration. Support external integrations by driving performance engineering, benchmarking, profiling, and optimization of APIs and driver paths in customer environments, including safety-critical use cases where applicable. What You Will Learn How user-mode and Linux kernel drivers are designed for high-performance AI hardware. How PCIe and other system interconnects are used to integrate accelerator hardware into production platforms. How hardware-software interfaces are defined to support scalable and portable systems. How performance is optimized across memory, compute, and communication layers. How safety and reliability requirements influence modern driver architecture, including in automotive and mission-critical systems. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II. Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability. Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST). What we need Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC. Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. What you will learn How to implement and close AI SoC partitions end-to-end, including power intent, timing, and physical signoff in a modern Synopsys-based flow. Deeper expertise across signoff domains: EM/IR, DRC/LVS, logical equivalence (LEC/Formality), and CDC-aware implementation on meaningful production blocks. Practical integration of analog/mixed-signal macros (PLL/DLL), DFT features (OCC/MBIST), and SoC interface IP within advanced physical design flows and collaborative tapeout environments. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures. This role is remote role open to any location in the U.S. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts. Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off. Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity). Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs. A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues. What We Need Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout. Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off. Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS. Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure. Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug). Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification. Bring a solid academic foundation: B.S./M.S. in EE/CE or related field. What You’ll Learn How to implement and close cutting-edge D2D interfaces in advanced multi-die/chiplet architectures. Advanced strategies for co-optimizing routing, power grid, and timing for high-speed links across dies. Deeper integration techniques working with analog PHY teams, including model handoff (LEF/LIB) and constraint-driven interface design. How to drive repeatable, scalable PD methodologies for high-speed interfaces that can be leveraged across future chiplets and products. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an experienced Analog Design Engineer to develop cutting-edge die-to-die chiplet PHY IP solutions that power the future of AI computing. You'll work at the forefront of deep sub-micron technologies, collaborating with circuit architects and cross-functional teams to push the boundaries of analog/mixed-signal design. If you have a proven track record of delivering production-quality silicon and want to innovate at the heart of next-generation interconnects, join our team. This role is remote, based out of any in North America. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are A Analog/Mixed-Signal Design Engineer to develop die-to-die chiplet PHY IP, including PLLs and key analog/mixed-signal blocks in deep sub-micron FinFET technologies. A hands-on owner for the full lifecycle: design, verification, layout interaction, tape-out, and silicon bring-up to production quality. A strong cross-functional partner who can work with architecture, analog, digital, verification, layout, and software teams to integrate and optimize AMS IP. What we need 10+ years of analog/mixed-signal IC design experience in FinFET, including PLL/AMS design, with an MSEE/PhD or equivalent background. Strong track record in production tape-outs, silicon bring-up/testing, and hands-on use of industry-standard EDA tools with close layout collaboration. Deep experience in high-speed datacomm/SerDes and die-to-die PHY design, including Tx/Rx, DDR, PCIe, and USB PHY components. Collaborative, self-driven engineer with expertise across key circuits such as bias generators, amplifiers, LDOs, ADCs/DACs, oscillators, switched-cap circuits, plus familiarity with high-speed digital and equalization techniques like CTLE, DFE, and de-emphasis. What you will learn How to push the limits of die-to-die chiplet PHY IP in advanced FinFET nodes, from architecture through high-volume production. How to co-optimize analog, digital, and layout to hit aggressive performance, power, and area targets in complex SoCs. Deeper expertise in high-speed I/O and PHY architectures, plus practical methodologies for scalable, reusable AMS IP across multiple products. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Analog Devices
Position available at official Analog Devices career portal. Requisition ID: undefined
Texas Instruments
Cadence Virtuoso layout implementation of precision analog power management ICs, ADC/DAC converters, and PLL clock generators. In-depth understanding of matching, latchup, and electromigration rules.
Graphcore
Senior Bring-Up and Characteristion Engineer Salary $156,500 - $211,700 + Phantom Equity + Benefits Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. We are looking for a Characterisation and Bring-Up engineer to work with Architecture, Silicon Engineering, Hardware Engineering, Operations (device manufacture) and Product teams to help create and execute the bring-up and characterisation of our cutting-edge silicon devices and system platforms. Graphcore design and develop leading edge silicon processors and high-power high-speed blade systems at the forefront of AI technology. As such you will need to develop a detailed understanding of our silicon and platform products. Your role will be to create and execute bring-up and characterisation plans of our silicon devices in systems to show that they will operate correctly over all conditions in the final product. You will concentrate on automated and manual testing of systems in the lab and datacentre. The results will be integrated with data from other teams to provide the complete characterisation solution for the product. For example, a large amount of device testing can be performed by the production test team using high-speed production test equipment. Responsibilities and Duties Understand the architecture and design of silicon devices and systems, and clearly document the requirements for characterisation Creation of product specific characterisation plans Liasing with engineering teams to understand what are tests are available for characterisation purposes and driving change where appropriate Create and maintain an automated system for running characterisation testing, capturing the results to a central database and performing data analysis Execution of manual characterisation tests where automation is not appropriate Report regularly on progress and issues during the characterisation Produce characterisation reports containing platform test results and feeding them up into the overall product characterisation report Essential skills A proven track record of delivering technical output, perhaps as an individual contributor, manager, or project manager Solid experience and understanding of silicon digital device design characterisation Knowledge of silicon process technology and how that impacts device performance at transistor and system level Knowledge of high-performance processor and system-on-chip systems Experience of high-speed digital interfaces, such as PCIe, Ethernet or DDR Knowledge of measurement automation and data analysis The ability to code or script automation and data analysis using appropriate coding languages such as Python, JMP for example An ability to work independently without daily oversight Desirable skills: Knowledge of PCBA and system level technologies Background knowledge of ATE systems and capabilities. Whilst you will not be directly involved with such testing, some of the characterisation work will be performed on such systems Benefits: In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
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