Steradian Semiconductors — VLSI Verification & Emulation Intern (6-11 Months)

Description

Gain hands-on experience at Steradian Semiconductors validating cutting-edge silicon IP and SoC blocks. Responsibilities: - Build constrained-random verification tests in SystemVerilog using UVM methodology. - Write assertions (SVA) and functional coverage metrics to achieve 100% verification signoff. - Debug simulation failures and participate in post-silicon laboratory bring-up sessions. Tech Stack: UVM, SystemVerilog, SVA, EDA Simulators (VCS / Questa / Xcelium), Python.

Eligibility

• Final-year B.Tech / M.Tech in ECE / VLSI / Embedded. Good knowledge of Verilog and OOP.