Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)

Executive Briefing & Key Highlights

Researchers at the University of California, Santa Cruz published a technical paper titled “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.” Abstract Excerpt: “Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power... » read more The p