Explore internships, research positions, jobs, scholarships and fellowships from top organizations across India and worldwide.
Graphcore
About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment. Responsibilities and Duties Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure. Support engineering bring-up activities, including component validation and firmware interaction testing. Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues. Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements. Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles. Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability. Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation. Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics. Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases. Candidate Profile Essential Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 7 years experience with server hardware architectures and board-level debugging. Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures. Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure. Strong collaboration skills and ability to work effectively in fast-paced engineering environments. Excellent written and verbal communication skills. Desirable Experience supporting prototype or pre-production hardware bring-up. Familiarity with data center facilities, including liquid cooling and power distribution systems. Experience using Python, Bash, or automation tools for hardware validation or troubleshooting. Exposure to structured failure analysis and reliability engineering methodologies. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking an experienced Staff UEFI Engineer to design, develop, and deploy UEFI-based firmware for Graphcore’s hyperscale AI server platforms. This role focuses on developing system firmware responsible for platform initialization, hardware configuration, and reliability features across large-scale data center deployments. The Team Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. The Firmware Engineering team develops the foundational firmware responsible for platform initialization, hardware configuration, and system reliability across Graphcore’s AI compute infrastructure. The team collaborates with silicon engineering, hardware design teams, BMC firmware teams, validation engineers, and platform architects to enable reliable server platform bring-up and operation. Responsibilities and Duties Design, develop, and deploy UEFI-based firmware for hyperscale server platforms. Collaborate with ODM partners throughout the design lifecycle from concept to mass production. Integrate UEFI firmware into CI/CD pipelines enabling automated builds, regression testing, and static analysis. Develop firmware functionality supporting platform initialization including CPU, memory, PCIe, and system interconnects. Implement system firmware security features including root of trust, secure boot chains, and signed firmware updates. Develop platform firmware features supporting server reliability, availability, and serviceability (RAS). Build firmware interfaces supporting telemetry, firmware updates, and system management capabilities. Collaborate with hardware, BMC, security, and validation teams to ensure full platform integration. Debug and perform root cause analysis for firmware and hardware issues across lab and production environments. Candidate Profile Essential Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 8+ years of experience developing UEFI or BIOS firmware for server platforms. Expertise with UEFI, TianoCore, and firmware architecture design. Strong experience developing firmware solutions for hyperscale or cloud data center environments. Strong programming skills in C/C++. Deep understanding of DDR memory training, cache coherency protocols, and PCIe subsystems. Strong knowledge of server platform architecture including power delivery, thermal management, sensors, and FRUs. Experience implementing CI/CD pipelines for firmware development. Experience debugging system firmware using logic analyzers, JTAG, GDB, and similar tools. Desirable Experience developing UEFI firmware for ARM-based server platforms. Experience with EDK II codebase development and upstream contribution. Experience working with ODM/JDM partners on server platform development programs. Experience delivering firmware for hyperscale cloud deployments and production environments. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment. Responsibilities and Duties Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure. Support engineering bring-up activities, including component validation and firmware interaction testing. Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues. Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements. Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles. Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability. Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation. Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics. Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases. Candidate Profile Essential Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 10 years experience with server hardware architectures and board-level debugging. Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures. Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure. Strong collaboration skills and ability to work effectively in fast-paced engineering environments. Excellent written and verbal communication skills. Desirable Experience supporting prototype or pre-production hardware bring-up. Familiarity with data center facilities, including liquid cooling and power distribution systems. Experience using Python, Bash, or automation tools for hardware validation or troubleshooting. Exposure to structured failure analysis and reliability engineering methodologies. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment. Responsibilities and Duties Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure. Support engineering bring-up activities, including component validation and firmware interaction testing. Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues. Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements. Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles. Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability. Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation. Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics. Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases. Candidate Profile Essential Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 12 years of strong experience with server hardware architectures and board-level debugging. Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures. Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure. Strong collaboration skills and ability to work effectively in fast-paced engineering environments. Excellent written and verbal communication skills. Desirable Experience supporting prototype or pre-production hardware bring-up. Familiarity with data center facilities, including liquid cooling and power distribution systems. Experience using Python, Bash, or automation tools for hardware validation or troubleshooting. Exposure to structured failure analysis and reliability engineering methodologies. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
Staff Embedded SW/FW Engineer (Bringup) Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon bringup sequences and test in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy configuration sequences and validation tests on first silicon and debug them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Candidate Profile Essential: Strong experience in Bare metal / embedded C/C++ Good knowledge of digital ASICs. Be highly motivated, a self starter, and a team player Ability to work across teams and programming languages to find root causes of deep and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Python, Linux Excellent communication skills and the ability to collaborate with others to solve problems. Excellent problem-solving, analytical & diagnostic skills Desirable: Driver level experience with one or more of the following is highly desirable: PCIe Ethernet Memory technologies (LPDDR, DDR, HBM, …) Other peripherals such as I2C, I3C, SPI, … Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable. Experience of Arm CPUs, System IP and debug tools. Experience of AMBA protocols. Understanding of ML applications and their workloads. Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support Benefits: In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us We are looking for a disciplined and dynamic Systems Engineer with focus on server CPU based system to join our growing compute rack validation team. Candidate we are seeking should have demonstrated work-experience in leading server rack and blade hardware systems deployment, hardware installation, and inventory management activities in the Austin, TX area. As a diligent leader in Systems Engineering, you will drive multiple aspects of post-silicon validation throughout the life cycle of the program. In this high visibility position, you will be part of a technical team chartered to innovate and improve system bring-up and enablement capabilities, as well as silicon and system validation to deliver the highest quality, industry leading technologies to market. Your technical leadership skills, systems engineering and hardware bring-up, validation and debug expertise will be necessary towards product development, definition, root cause and resolution. Your agility and collaborative approach will be essential to work within System Validation & other engineering teams (System Architects, SoC and Rack FW etc). The ideal candidate will be driving key areas around at-scale system validation including ARM based server and rack level systems bring-up (nodes and rack level systems). Candidate will be immersed in challenging system enablement work, ramp-up post-silicon capabilities in engineering lab environments, validation tests execution/triage. The candidate will be leading contributor towards state-of-the-art HW bring-up and lab capabilities for Grapchore’s system engineering. The candidate should be able to work in a global environment while maintaining a synergetic culture. Primary Responsibilities: Install, configure, commission (and decommission if needed) blade servers, chassis, switches, and supporting infrastructure. Lead rack and stack activities, including mounting equipment, cable management, and labelling. Execute hardware upgrades, replacements, and troubleshooting of server and network components. Maintain accurate asset records within DCIM platforms and inventory management systems. Conduct physical audits and reconcile inventory discrepancies. Track hardware movements, deployments, and decommissions through established change management processes. Document installation procedures, rack layouts, cabling diagrams, and inventory updates. Support data center migration, expansion, and refresh projects. Collaborate with engineering, operations, logistics, and project management teams. Adhere to all data center safety, security, and operational standards. Develop, setup and scale key methodologies for at-scale test execution, lab HW and system SW capabilities as well as system visibilities and debug tools necessary for successful system (HW/SW/FW) bring-up and system validation at blade and rack level for AI compute rack. Ability to work independently in a production ready environment, and a commitment tomaintaining accurate inventory and asset records. Triage issues found during server rack validation bring-up, Post-Silicon Validation, and production phases of the program. Ensure issues are solved on time with quality. Lead test execution of key domains within AI compute solutions like CPU, GPU, memory, HBM, IO etc. Drive technical innovation to improve capabilities across system validation, including tools, script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives. Qualifications: Strong analytical/problem-solving skills and pronounced attention to details Experience in Blade server installation and maintenance (Cisco UCS, HPE Synergy, Dell MX, or similar). Rack and stack deployments in enterprise or hyperscale environments. Copper and fiber cabling installation and management. DCIM and asset management platforms. Strong understanding of server, storage, and networking hardware. Experience performing inventory audits and maintaining asset accuracy. Ability to read rack elevation diagrams, cabling schematics, and deployment documentation. Familiarity with ticketing and change management systems. Exposure to Linux (ubuntu) OS bootable images and system firmware basics for image building, provisioning and firmware flashing. Exposure to automation testing, to enable execution of hardware acceptance tests, best-known-config testing etc. Exposure to python script development and execution. Proven experience in understanding, defining and enabling storage (storage rack), networking capabilities (network rack, DNS, DHCP etc) in a lab environment to help add end-to-end validation and debug capabilities for rack and blade validation. Excellent communication and coordination skills. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Technical leadership: capable of championing new tools, methods, and capabilities to drive platform validation improvements in schedule, quality, or coverage. Experience working with data center technical staff, 3rd party vendors, ODMs etc throughout the life cycle of server system product development. Must be a self-starter, and able to independently drive tasks to completion Preferred Qualifications: Masters or PhD in Electrical Engineering, Computer Engineering or a related field. 10+ years of work experience demonstrating working on complex systems engineering challenges to validate and debug HW-FW-SW challenges in a server compute rack or data center blade environment. Experience designing and deploying modern AI/ML rack scale systems Knowledge of industry standards and best practices for hardware development Familiarity with emerging technologies in AI and Data Center infrastructure. Comfortable meeting, engaging and collaborating with ODM partners and staffing vendors across the globe. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
We are looking for a disciplined and dynamic, Lead System Engineer – compute blade and rack Validation to join our growing compute rack validation team. As a diligent leader in Systems Engineering, you will drive multiple aspects of validation throughout the life cycle of the program. In this high visibility position, you will be part of a leading team to innovate and improve system bring-up and enablement abilities, as well as silicon and system validation to deliver the highest quality, industry leading technologies to market. Your technical leadership skills, validation and debug expertise will be necessary towards product development, definition, root cause and resolution. Your agility and collaborative approach will be essential to work within System Validation & other engineering teams (System Architects, SoC and Rack FW etc). The technical leader will be driving keys areas of system validation including leading first silicon & system bring-up (nodes and rack level systems) - rack level systems and blades will be based of ARM server architecture. Candidate will be immersed in challenging system enablement work, system validation (end-to-end) methodology, tests development and execution as well as triage/debug of critical issues to meet critical program milestones at POR quality. The candidate will also be a key contributor to state-of-the-art HW and lab capabilities for Grapchore’s system engineering. The candidate should be able to work in a global environment while maintaining a synergetic culture. Primary Responsibilities: Lead the systemenablement (including first silicon and other FW components) to ensure system capabilities are brought up as per plan of record and system architecture spec. Drive organization wide methodology for Firmware integration and best known configuration (HW/FW/SW) usage model by leading the release of deployment ready solutions. Develop key methodologies, lab HW and system SW capabilitiesas well as system visibilities and debug tools necessary for successful system (HW/SW/FW) bring-up and system validation at blade and rack level for AI compute rack. Triageissues found during server rack validation bring-up, Post-Silicon Validation, and production phases of the program. Ensure issues are solved on time with quality. Develop and own test plans,lead test case development and execution of key domains within AI compute solutions like CPU, GPU, memory, HBM, IO etc. Drive technical innovation to improve capabilities acrosssystem validation, including tool, script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives. Qualifications: Strong analytical/problem-solving skills and pronounced attention to details Extensive experience in validation roles involvingfirst silicon and system bring up, OS, FW, Silicon, and HW Understanding of PC industry standardbuses and their software stack, such as PCIe, CXL. Proven experience in understanding,defining and enabling storage (storage rack), networking capabilities (network rack, DNS, DHCP etc) in a lab environment to help add end-to-end validation and debug capabilities for rack and blade validation. Strong knowledge ofARM CPU or X86 architecture, SoC design, memory, RAS & power management as well as HW/SW based tools, and revision control systems. Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, DeviceDrivers and System BIOS interactions. Excellent communication and coordination skills. Detailed oriented, highly organized, able to prioritize, and juggle multiple workstreams to tight deadlines. Technical leadership: capable of championing new tools, methods, and capabilities to drive platform validation improvements in schedule, quality, or coverage. Deep experience with Linux and Windows Operating Systems, Hypervisors (VMware, KVM, Hyper-V, etc.), and development and certification processes of these environments Experience in technical program management. A thorough understanding of datacenter industry technologies and their software stack. Must be a self-starter, and able to independently drive tasks to completion Preferred Qualifications: Mastersor PhD in Electrical Engineering, Computer Engineering or a related 14+ years of work experience demonstrating working on complex systems engineering challenges to validate and debug HW-FW-SW challenges in a server compute rack or data center blade environment. Experience designing and deploying modern AI/ML rack scale systems Knowledge of industry standards and best practices for hardwaredevelopment Familiarity with emerging technologies in AI andData Center Comfortable meeting,engaging and collaborating with ODM partners across the globe. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking an experienced Senior UEFI Engineer to design, develop, and deploy UEFI-based firmware for Graphcore’s hyperscale AI server platforms. This role focuses on developing system firmware responsible for platform initialization, hardware configuration, and reliability features across large-scale data center deployments. The Team Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. The Firmware Engineering team develops the foundational firmware responsible for platform initialization, hardware configuration, and system reliability across Graphcore’s AI compute infrastructure. The team collaborates with silicon engineering, hardware design teams, BMC firmware teams, validation engineers, and platform architects to enable reliable server platform bring-up and operation. Responsibilities and Duties Design, develop, and deploy UEFI-based firmware for hyperscale server platforms. Collaborate with ODM partners throughout the design lifecycle from concept to mass production. Integrate UEFI firmware into CI/CD pipelines enabling automated builds, regression testing, and static analysis. Develop firmware functionality supporting platform initialization including CPU, memory, PCIe, and system interconnects. Implement system firmware security features including root of trust, secure boot chains, and signed firmware updates. Develop platform firmware features supporting server reliability, availability, and serviceability (RAS). Build firmware interfaces supporting telemetry, firmware updates, and system management capabilities. Collaborate with hardware, BMC, security, and validation teams to ensure full platform integration. Debug and perform root cause analysis for firmware and hardware issues across lab and production environments. Candidate Profile Essential Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 6+ years of experience developing UEFI or BIOS firmware for server platforms. Expertise with UEFI, TianoCore, and firmware architecture design. Strong experience developing firmware solutions for hyperscale or cloud data center environments. Strong programming skills in C/C++. Deep understanding of DDR memory training, cache coherency protocols, and PCIe subsystems. Strong knowledge of server platform architecture including power delivery, thermal management, sensors, and FRUs. Experience implementing CI/CD pipelines for firmware development. Experience debugging system firmware using logic analyzers, JTAG, GDB, and similar tools. Desirable Experience developing UEFI firmware for ARM-based server platforms. Experience with EDK II codebase development and upstream contribution. Experience working with ODM/JDM partners on server platform development programs. Experience delivering firmware for hyperscale cloud deployments and production environments. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. Job Summary We are seeking a Senior System Validation Engineer to design and implement validation tests for Arm-based data center SoCs using a combination of open-source benchmarking tools and custom micro-benchmarks. Define test cases, tune workload parameters, and use Python to automate and analyze validation across processing units, system memory, communication links, and PCI Express components. The Team The Systems Validation team validates Graphcore’s AI compute platforms across hardware, firmware, and software domains. Responsibilities and Duties Translate hardware features into structured, parameterized test cases, including: Objectives, workload models, parameters, metrics, and pass/fail criteria. Use and tune open-source tools such as: Stress-ng, fio, iperf, sysbench, Imbench Define workload parameters: Concurrency (threads/cores), memory footprint, access patterns Queue depth, block size, CPU/NUMA affinity. Design and execute validation scenarios: Functional, performance, stress, and corner-case testing. Validate across domains: CPU scaling and cache behavior Memory (DDR/HBM) bandwidth, latency, and NUMA effects Interconnect contention under multi-core load PCIe/I-O throughput, latency, and multi-device scenarios Develop custom micro-benchmarks (C/C++) when existing tools are insufficient Use Python to: Automate test execution and orchestration Implement parameter sweeps and test matrices Parse, analyze, and visualize results. Debug system behavior and performance issues in collaboration with hardware and firmware teams Candidate Profile Essential: Strong background in Linux systems and low-level performance analysis Experience in system validation, benchmarking, or performance testing Solid understanding of one or more domains: CPU architecture, memory systems, or PCIe Experience using benchmarking tools (stress-ng, fio, iperf, etc.) Ability to define test cases, parameters, and workload models Proficiency in Python (essential) for automation, orchestration, and data analysis Programming experience in C/C++ for micro-benchmark development Desirable: Experience with Arm-based platforms Strong programming skills in C/C++ and Python for system-level development and automation Familiarity with performance tools (perf, numactl, taskset) Experience with large-scale or high core-count systems USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Senior Firmware Validation Engineer to support validation and quality assurance for the rack-level firmware stack across Graphcore’s ARM-based server platforms. This role focuses on validating firmware components including SoC firmware (EDK II/UEFI), OpenBMC firmware, rack management services, and platform-level infrastructure used in hyperscale AI server deployments. The Team Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. The Platform Validation team ensures the reliability and quality of Graphcore’s firmware and system software stack across server nodes and rack-scale AI infrastructure. The team collaborates closely with firmware engineering, silicon teams, hardware engineering, and ODM partners to validate complex platform management stacks and ensure production readiness. Responsibilities and Duties Define and execute validation strategy for rack-level firmware stacks across ARM server platforms. Develop validation plans and automated test frameworks for platform bring-up and firmware lifecycle management. Integrate automated test cases for rack-level firmware components into CI/CD pipelines. Validate firmware update frameworks including signed updates, redundancy mechanisms, and rollback protection. Drive validation of platform security features including Root of Trust, secure boot, and TPM integration. Participate in system-level debugging and root cause analysis across firmware, hardware, and platform integration. Develop automation frameworks and regression testing pipelines supporting firmware validation. Collaborate with silicon vendors, ODM partners, and platform engineering teams during bring-up and manufacturing ramp. Candidate Profile Essential Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. 6+ years of experience in firmware or platform validation for server or data center systems. Experience validating ARM server firmware stacks including UEFI/EDK II and OpenBMC platforms. Strong understanding of server architecture including power delivery, thermals, networking, and rack infrastructure. Experience validating firmware security features including Root of Trust and secure boot. Strong familiarity with firmware lifecycle management and firmware update frameworks. Experience building automation frameworks and CI/CD pipelines for firmware validation. Desirable Experience validating rack-scale firmware platforms in hyperscale or AI cloud environments. Hands-on experience with EDK II/UEFI validation and OpenBMC system testing. Experience validating firmware for liquid-cooled or high-density server platforms. Experience building hardware-in-the-loop (HIL) or rack-level automated validation environments. Experience validating high-speed interconnects such as PCIe in large-scale deployments. Familiarity with hardware debug tools including JTAG, GDB, and logic analyzers. Experience validating platform management protocols such as Redfish, PLDM, MCTP, and IPMI. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The Team The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems. The team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure. Responsibilities and Duties Lead post-silicon debug and validation activities for AI compute silicon and platform technologies Contribute to debug and validation activities across multiple projects and milestones Drive prioritisation, planning and execution of debug and validation activities across multiple projects and milestones Investigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validation Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency Collaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actions Drive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditions Develop and enhance automated debug, regression and validation infrastructure using Python and related technologies Analyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issues Support development of validation tests, debug tooling and custom diagnostics to improve coverage and observability Define validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysis Drive continuous improvement of debug processes, validation methodologies and engineering workflows Communicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholders Support silicon readiness reviews and contribute to product quality and release decisions Contribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows Candidate Profile Essential: Strong experience in bare metal environments Good knowledge of SoC and platform architectures Expertise in debug infrastructure and post-silicon debug methodologies Strong programming skills in Python, C, or debug scripting languages such as CMM Highly motivated self-starter with a collaborative and team-oriented approach Ability to work across teams and programming languages to identify root causes of deep and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Strong Linux and Python experience Exceptional communication skills and the ability to collaborate effectively to solve complex problems Excellent problem-solving, analytical and diagnostic skills Deep knowledge of scan, DFT, JTAG and trace infrastructure Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniques Ability to work independently on technically complex debug and validation activities across hardware, firmware and software domains Desirable Understanding of DFT flows from insertion through post-silicon validation Experience developing tooling for parsing and analysing debug data, including scan dump parsing Driver-level experience with one or more of the following technologies: PCIe Ethernet Memory technologies including LPDDR, DDR and HBM Peripheral interfaces such as I2C, I3C and SPI Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STM Good knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocols Experience with Arm CPU architectures, system IP and associated debug tooling Experience with AMBA protocols Understanding of ML applications and associated workloads Experience in characterization, failure analysis, test development, statistical analysis and customer support
Graphcore
Principal Post Silicon Validation Engineer (Bringup) Salary $241,100 - $326,100 + Phantom Equity + Benefits Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing. We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy silicon validation tests on first silicon and debugging them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Essential skills: Strong experience in Bare metal / embedded C/C++ Good knowledge of digital ASICs Be highly motivated, a self starter, and a team player Ability to work across teams and programming languages to find root causes of deep and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Python, Linux Excellent communication skills and the ability to collaborate with others to solve problems Excellent problem-solving, analytical & diagnostic skills Desirable skills: Driver level experience with one or more of the following is highly desirable: PCIe Ethernet Memory technologies (LPDDR, DDR, HBM, …) Other peripherals such as I2C, I3C, SPI, … Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable Experience of Arm CPUs, System IP and debug tools Experience of AMBA protocols Understanding of ML applications and their workloads Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
Principal Embedded SW/FW Engineer (Bringup) - Bengaluru, multiple vacancies Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms. You will play a key role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy silicon validation tests on first silicon and debugging them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Candidate Profile Essential: Understanding of ML applications and their workloads A self-starter who can apply independent judgement A team player able to lead and support colleagues with difficult concepts Strong experience in Bare metal / embedded C/C++ Excellent problem-solving, analytical & diagnostic skills Ability to work across teams and programming languages to find root causes of critical and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Python, Linux Excellent communication skills and the ability to explain difficult concepts to resolve issues Desirable 10+ years experience Experience building and leading, multi-site teams Driver level experience with one or more of the following is highly desirable: PCIe Ethernet Memory technologies (LPDDR, DDR, HBM, …) Other peripherals such as I2C, I3C, SPI, … Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable. Experience of Arm CPUs, System IP and debug tools. Experience of AMBA protocols. Experience in Characterization, Failure Analysis, Test Development, Statistical analysis,
Graphcore
Principal Embedded SW/FW Engineer (Bringup) - Austin, Tx, USA Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms. You will play a key role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy silicon validation tests on first silicon and debugging them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Candidate Profile Essential: Understanding of ML applications and their workloads A self-starter who can apply independent judgement A team player able to lead and support colleagues with difficult concepts Strong experience in Bare metal / embedded C/C++ Excellent problem-solving, analytical & diagnostic skills Ability to work across teams and programming languages to find root causes of critical and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Python, Linux Excellent communication skills and the ability to explain difficult concepts to resolve issues Desirable 5 to 10 years’ experience Experience building and leading, multi-site teams Driver level experience with one or more of the following is highly desirable: PCIe Ethernet Memory technologies (LPDDR, DDR, HBM, …) Other peripherals such as I2C, I3C, SPI, … Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable. Experience of Arm CPUs, System IP and debug tools. Experience of AMBA protocols. Experience in Characterization, Failure Analysis, Test Development, Statistical analysis,
Graphcore
About Graphcore Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. The Role: We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy silicon validation tests on first silicon and debugging them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Essential skills: Strong experience in Bare metal / embedded C/C++ Good knowledge of digital ASICs Be highly motivated, a self starter, and a team player Ability to work across teams and programming languages to find root causes of deep and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Python, Linux Excellent communication skills and the ability to collaborate with others to solve problems Excellent problem-solving, analytical & diagnostic skills Desirable skills: Driver level experience with one or more of the following is highly desirable: PCIe Ethernet Memory technologies (LPDDR, DDR, HBM, …) Other peripherals such as I2C, I3C, SPI, … Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable Experience of Arm CPUs, System IP and debug tools Experience of AMBA protocols Understanding of ML applications and their workloads Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support Benefits: In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Graphcore
About us At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary Reporting to Senior Director of Post Silicon Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. You will lead teams passionate about identifying, reproducing, analyzing, and resolving complex silicon, firmware, and system-level issues during bring-up, characterization, and product readiness. This role combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering fields. The Team The Post-Silicon Debug and Validation team manages bring-up, fault diagnosis, and validation of Graphcore silicon and systems. Our team participates throughout the entire product lifecycle, supporting initial silicon bring-up, subsystem validation, system integration, and production readiness tasks. We coordinate closely with hardware, firmware, software, and systems teams to examine complex failures, develop debug strategies, and advance validation infrastructure. Responsibilities and Duties Lead post-silicon debugging and validation efforts for AI compute silicon and platform technologies Contribute to debug and validation activities across multiple projects and achievements Analyze and address intricate silicon, firmware, software, and system-level problems during bring-up and validation Develop structured debug methodologies and failure analysis processes to improve issue resolution efficiency Work in close partnership with architecture, RTL, firmware, software, and systems engineering groups to determine root causes and carry out corrective measures Drive debug of CPU, memory, interconnect, and high-speed I/O subsystems under functional, stress, and workload conditions Develop and improve automated debug, regression, and validation infrastructure using Python and related technologies Analyze logs, traces, telemetry, and hardware data to isolate and characterize system failures and performance issues Support development of validation tests, debug tooling, and custom diagnostics to improve coverage and observability Define validation metrics, debug workflows, and reporting standards to ensure consistent and repeatable analysis Communicate technical risks, status, and recommendations clearly to engineering leadership and cross-functional collaborators Support silicon readiness reviews and contribute to product quality and release decisions Contribute to continuous improvement of debug methodologies, validation infrastructure, and engineering workflows Candidate Profile Essential: Strong experience in bare metal environments Strong understanding of SoC and platform architectures Expertise in debug infrastructure and post-silicon debug methodologies Strong programming skills in Python, C, or debug scripting languages such as CMM or equivalent experience Highly motivated self-starter with a collaborative and team-oriented approach Ability to collaborate across teams and programming languages to uncover root causes of deep and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Strong Linux and Python experience Outstanding communication skills and the ability to collaborate effectively to solve complex problems Excellent problem-solving, analytical, and diagnostic skills Deep knowledge of scan, DFT, JTAG, and trace infrastructure Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies, and system-level debug techniques Capability to operate autonomously on technically intricate debug and validation tasks spanning hardware, firmware, and software areas Desirable Understanding of DFT flows from insertion through post-silicon validation Experience developing tooling for parsing and analyzing debug data, including scan dump parsing Driver-level experience with one or more of the following technologies: PCIe, Ethernet, Memory technologies including LPDDR, DDR, and HBM, Peripheral interfaces such as I2C, I3C, and SPI Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB, and STM or equivalent experience Strong understanding of mixed-signal components like PLLs, high-speed PHYs, and IC control/communication protocols Experience with Arm CPU architectures, system IP, and associated debug tooling Experience with AMBA protocols Understanding of ML applications and associated workloads Experience in characterization, failure analysis, test development, statistical analysis, and customer support Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly technical Senior Staff/Principal Engineer to lead the porting and enablement of critical AI workloads. You will be a primary driver in migrating compute workloads to RISC-V architectures, ensuring our hardware is optimized for real-world application performance. The ideal candidate has a strong background in DevOps, workload porting, or application enablement. While this is an individual contributor role at its core, you will have the opportunity to grow and lead a small, specialized team over time as our workload migration efforts scale. This role is remote, based in the United States or Australia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Technical Catalyst: You thrive on the challenge of driving AI hardware porting to RISC-V and making complex software stacks run efficiently on new hardware. Systems Expert: You possess deep knowledge of system software, compilers, or low-level OS internals. You are an expert in ARM or x86 environments and are ready to apply those skills to the RISC-V frontier. A Project Driver: You have the technical authority to lead the implementation of a compute migration to RISC-V through strategic IT and DevOps enablement. Collaborative & Cross-Functional: You enjoy acting as the "technical glue" between IT, DevOps, and AI teams, coordinating complex efforts across boundaries to ensure seamless workload transitions. Architecture Agnostic: You are a systems thinker who understands how to bridge the gap between infrastructure and core silicon engineering. What We Need Education: BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field. Workload Expertise: Extensive experience in workload porting, DevOps engineering, or application enablement. Systems Fluency: Strong familiarity with CPU architectures and systems design, with a proven track record of troubleshooting and optimizing performance across new architectures. Leadership Qualities: Ability to coordinate across multiple technical teams and the potential to mentor or grow a small engineering pod. Execution Focus: A mindset geared toward technical delivery and methodology development rather than broad community networking. What You Will Learn Gain deep expertise in bleeding-edge RISC-V system software across server and AI-accelerated environments. Directly influence an upcoming project, a high-visibility initiative shaping the future of our internal compute infrastructure. Work at the intersection of AI/ML workloads and hardware/software co-design. Shape the technical roadmap for how the industry adopts RISC-V for high-performance compute. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an Senior Engineer to develop and optimize the software stack for our IP customers, enabling them to successfully integrate our AI and RISC-V hardware into their systems. In this role, you will build and support a versatile range of software components, from bare-metal firmware and drivers to system-level tools and APIs, ensuring a seamless customer experience. You will partner closely with hardware engineering, IP delivery, customer support, and product teams to deliver robust, scalable, and high-performance software solutions tailored to diverse customer architectures. Success in this role requires adaptability, strong system-level debugging skills, and the ability to bridge the gap between complex hardware IP and user-friendly software integration. This role is hybrid, based out of Toronto, ON, Austin, TX, or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced software engineer with a strong foundation in C/C++, system programming, and low-level software design. Parallel processing, SIMD architectures (SSE, AVX, Arm Neon), GPU programming (CUDA, OpenCL) a plus. Background in firmware, device drivers, embedded systems, or hardware-software co-design. Skilled at navigating and troubleshooting complex, full-stack software environments. Known for working effectively with cross-functional teams and external customers to resolve integration challenges. Able to balance versatile, hands-on coding with high-level architectural problem-solving. What We Need Develop, optimize, and maintain software components for Tenstorrent’s hardware IP offerings. Define and build reference software, SDKs, and toolchains to streamline the customer integration process. Diagnose and resolve complex hardware/software interaction issues during customer bring-up and deployment. Drive the creation of high-quality documentation, test suites, and integration guides for IP software deliverables. Partner cross-functionally with hardware and architecture teams to ensure future IP designs are optimized for software usability. What You Will Learn How to build and deploy robust software stacks for cutting-edge AI and RISC-V silicon IP. How to drive successful hardware-software integration across a diverse range of customer environments and architectures. Firsthand exposure to the complete silicon IP lifecycle, from initial bring-up to massive-scale customer deployment. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the unit specification, RTL design, and unit verification. This role is Remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Key Responsibilities: RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure. RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA. AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process. Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team. Qualifications: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V. Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…) Deep understanding of CPU microarchitecture and PPA trade-off. Basic understanding of RISC-V Architecture including V-extension is preferred. Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL. Excellent problem-solving abilities and analytical skills. Strong communication skills, with the ability to convey complex technical concepts to diverse audiences. Ability to work collaboratively in a team-oriented environment and across multiple disciplines. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a Verification Lead for our next-generation AI hardware. You’ll guide a top-tier team of Verification Engineers, shaping test strategies to validate functionality and performance of our AI core. This role requires expertise in AI-specific data types, common AI data-movement compute patterns, and on-chip network validation, combined with strong leadership and collaboration skills. This role is hybrid, based out Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Seasoned Verification Leader: An experienced ASIC/SoC lead with proven track record of leading teams through complex tape-outs. An AI Hardware Specialist: An expert in the nuances of high-performance compute, specifically focused on AI/ML architectures and the intricacies of tensor-based operations. A Systems Architect at Heart: A strategist who views verification through a system-level lens, ensuring that hardware, software, and on-chip networks (NoC) harmonize perfectly. A Technical Mentor: A hands-on guide proficient in UVM, SystemVerilog, and cocotb, dedicated to elevating team capabilities and driving rigorous coverage-driven methodologies. What We Need Strategic AI Verification: Expertise in architecting verification plans for mixed-precision data types (FP8, BF16, INT8) and validating the accuracy of complex AI transformations. High-Performance NoC Expertise: Deep experience benchmarking on-chip networks under high-demand traffic, ensuring throughput, bandwidth, and congestion management meet peak requirements. Resiliency & Error Injection: A proactive approach to system stability, implementing robust concurrency controls and multi-core synchronization to handle edge-case failures. Platform-Agnostic Methodology: The ability to develop portable test strategies that scale seamlessly from subsystem-level simulations to FPGA and final Silicon. Cross-Functional Synergy: A collaborative mindset that bridges the gap between hardware architecture and software requirements to ensure performance targets are met. What You Will Learn Next-Gen AI/ML Tooling: Integrating your specific advanced automation frameworks and emerging AI-driven verification techniques into the existing lifecycle. Evolving Workload Dynamics: Gaining a deeper understanding of your proprietary AI workloads and how they stress memory access patterns uniquely within your architecture. Project-Specific Performance Bottlenecks: Identifying and mastering the unique architectural constraints of your specific SoC to push bandwidth limits further. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU design verification, test generation, or closely related CPU validation work. You have led development of test generators for x86, ARM, or RISC-V ISA environments. You understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture. You are comfortable building tools, stimulus, and automation that scale verification across large CPU programs. You communicate clearly across design, DV, architecture, emulation, and post-silicon teams. What We Need Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores. Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in both pre-silicon and post-silicon Develop directed and randomized stimulus that targets architectural corner cases, instruction interactions, and complex CPU behavior. Support RISC-V certification work, including test content, compliance flows, debug, and closure. Guide a small team of 4-5 engineers while staying hands-on with implementation, debug, and verification execution. What You Will Learn How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters. Techniques for scaling CPU test generator infrastructure across core, cluster, and chip-level environments. Ways to apply ISA-driven stimulus to complex CPU verification and debug workflows. Techniques for supporting RISC-V certification alongside internal verification requirements. How to scale coverage, debug, and generator methodology across multiple CPU programs within Tenstorrent’s broader compute roadmap. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
ARM Holdings
Career opportunity at ARM Holdings.
ARM Holdings
Career opportunity at ARM Holdings.
ARM Holdings
Career opportunity at ARM Holdings.
Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller. You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 3–6 years of experience in ASIC design, with expertise in microarchitecture and RTL for complex subsystems. Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes. Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI). Awareness of functional safety (ISO 26262) practices in hardware design. What We Need Ability to own microarchitecture definition and RTL development of Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller. Experience driving verification closure, performance debug, synthesis, timing, and power optimization. Strong skills in LINT, CDC/RDC, and power intent checks. Proficiency with DV and analysis tools like Verdi, NCSIM, and power estimation tools. Hands-on experience in design-for-power, debug, and test methodologies. What You Will Learn Building power-efficient, high-performance subsystems for advanced RISC-V/ARM architectures. Cross-functional collaboration from concept to silicon bring-up. Enhancing subsystem performance through innovative power, performance, and area optimizations. Leadership and mentorship experience by guiding junior design engineers. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
ARM Holdings
Career opportunity at ARM Holdings.
Graphcore
Senior Post Silicon Validation Engineer (Bringup) Salary $156,500 - $211,700 + Phantom Equity + Benefits Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin which will play a central role in Graphcore's work building the future of AI computing. We are looking to hire Post-Silicon Validation Engineers to join our collaborative, cross-functional development team validating cutting edge, high performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Post-Silicon Validation team sits within the Architecture and Validation team, we are responsible for validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and also supporting the Silicon Characterisation team. Responsibilities and Duties Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon Deploy silicon validation tests on first silicon and debugging them Develop automated test framework and regression test suites in Python to optimize validation efficiency Collaborate closely with engineers from many other disciplines on a variety of topics Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies Analyse test results, identify and debug failures/defects Contribute to shared test and validation infrastructure Provide feedback to architects Essential skills: Strong experience in Bare metal / embedded C/C++ Good knowledge of digital ASICs Be highly motivated, a self starter, and a team player Ability to work across teams and programming languages to find root causes of deep and complex issues Experience of the post-silicon validation process applied in digital ASIC environments Python, Linux Excellent communication skills and the ability to collaborate with others to solve problems Excellent problem-solving, analytical & diagnostic skills Desirable skills: Driver level experience with one or more of the following is highly desirable: PCIe Ethernet Memory technologies (LPDDR, DDR, HBM, …) Other peripherals such as I2C, I3C, SPI, … Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable Experience of Arm CPUs, System IP and debug tools Experience of AMBA protocols Understanding of ML applications and their workloads Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.
Showing 1–8 of 29 opportunities
Get the latest internships, jobs, scholarships and research opportunities delivered to your inbox.
Get early access to verified notifications & deadlines.
Only relevant and verified career opportunities.
We value your inbox. Zero marketing clutter.
10,000+ students & scholars actively advancing.
